The present invention relates to a semiconductor device and its manufacturing technique. In particular, it relates to a technique effective to be applied to a semiconductor device in which semiconductor chips arranged side by side are electrically coupled via a wire.
Japanese Patent Laid-open No. 2004-356382 (Patent Document 1) describes a semiconductor device in which two semiconductor chips arranged adjacent to each other, in a planar manner, over one die pad are electrically coupled via a wire.
Also, Japanese Patent Laid-open No. 2011-124487 (Patent document 2) describes a semiconductor device in which two semiconductor chips arranged adjacent to each other, in a planar manner, over a wiring substrate are electrically coupled via a wire.
[Patent Document 1]
Japanese Patent Laid-open No. 2004-356382
[Patent Document 2]
Japanese Patent Laid-open No. 2011-124487